The present invention relates generally to three dimensional (3D) integrated circuits, and more particularly to 3D integrated circuits with through silicon vias.
Since the invention of the integrated circuit, the semiconductor industry has experienced continual rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, allowing for the integration of more components into a given area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
An additional limitation comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit resistance-capacitance (RC) delay and power consumption increase.
Three-dimensional integrated circuits are therefore created to resolve the above-discussed limitations. In a typical formation process of 3D integrated circuits, two wafers, each including an integrated circuit, are formed. The wafers are then bonded with the devices aligned. Deep vias are then formed to interconnect devices on the first and second wafers.
Much higher device density has been achieved using 3D integrated circuit technology. As a result, the total wire length is significantly reduced. The number of vias is also reduced. Accordingly, 3D integrated circuit technology has the potential of being the mainstream technology of the next generation.
Various 3D integrated circuits have been proposed by Chan et al. U.S. Application Publication 2005/0067620, Enquist et al. U.S. Patent Application Publication 2007/0037379, Chen et al. U.S. Patent Application Publication 2007/0145367, Yu et al. U.S. Patent Application Publication 2008/0142990, Luo et al. U.S. Patent Application Publication 2008/0153187, Inoue et al. U.S. Pat. No. 6,627,518, Chan et al. U.S. Pat. No. 6,821,826, Morrow et al. U.S. Pat. No. 7,056,813, Vanhaelemeersch et al. U.S. Pat. No. 7,338,896, Pogge et al. U.S. Pat. No. 7,354,798, Sankarapillai et al. U.S. Pat. No. 7,381,629, Koyanagi et al., “Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections”, IEEE Transactions on Electron Devices, 53, No. 11 (November 2006), pp 2799-2808, and Burns et al., “A Wafer-Scale 3-D Circuit Integration Technology”, IEEE Transactions on Electron Devices, 53, No. 10 (October 2006), pp 2507-2516, the disclosures of which are incorporated by reference herein.
Of the foregoing references, Morrow et al. discloses forming backside through via connections. Chan et al. U.S. Patent Application Publication 2005/0067620 and U.S. Pat. No. 6,821,826 disclose the necessity of forming two vias to connect the wiring on joined integrated circuits. Endquist et al. U.S. Patent Application Publication 2007/0037379 and the Burns et al. paper disclose the formation of through vias that connect two levels of metal wherein the vias are formed through the silicon after the wafers are bonded.